In the development of circuitry and control systems for digital devices, it has long been a problem as to how to sufficiently implement logic circuitry in order to provide control signals to regulate and control associated circuitry or to control a target digital device.
In earlier periods of technology, analog signals and analog circuitry were used to generate analog signals which could be transmitted to analog target devices in order to control their operation. With the advent of digital logic circuitry and with the great flexibility for usage with Field Programmable Gate Arrays (FPGAs), and also with the use of Application Specific Integrated Circuits (ASICs), it is now possible that great efficiencies can be provided in using digital busses carrying multiple-bit digital signals which then can be digitally processed in order to provide desired or required output signals or control signals for target digital devices.
Many of the input/output and control signals in digital circuitry will be seen to have mathematical relationships to each other. Thus, with the use of what are called functional relationship generators, which can efficiently be implemented in digital circuitry, it can be found that there is considerably greater efficiency in using various signals and parameters in order to develop a desired output control signal for a controlled module.
The presently described system and method shows how mathematical and functional relationships of digital signals in the electronic circuitry can be represented by the use of simple standardized logic design elements. These systems and methods can be build into simple, industry-standard programmable logic elements, for example, such as PALs (Programmable Logic Arrays), or Field Programmable Gate Arrays (FPGAs).
The above cited co-pending applications illustrate various techniques for implementation in digital logic of certain electrical functional relationships. The above cited co-pending applications are included herein by reference.
General overview:
FIG. 1A shows the basic diagram of a simple control system. The device 10(D) is the device under the control of a control system 8,H. The device under control 10(D) can exist in many different types of mechanisms, for example, the device D may be a physically positioning motor mechanism. Whatever the device 10 is, in any given situation, it produces some required action which is denoted in FIG. 1A as the desired action F.sub.r.
Device 10(D) is controlled by the control system output signal on line 9o with a signal designated Y.sub.0 which causes the device D(10) to take action toward a desired condition, parameter or position. Within the control system 8,H, there is a driver block 9(E) which creates and drives the output signal Y.sub.0. The driver unit 9 uses its input signal Y on line 8x in order to create the output signal Y.sub.0. Additionally, a functional generator circuit 4(G) creates the different signal Y from two inputs to the functional generator 4(G). The first input to functional generator G(4) is from outside the control system on line 2 and is designated as input signal, A. This is the main input control signal designated A. The second input signal is actually feedback from the device under control 10(D). This signal is in some way proportional to the activity or existing condition operating within the device 10(D).
If, for example, it is assumed that the device under control D(10) is a motor used to adjust the physical position of some object, then the signal Y.sub.0 would be a voltage of the correct amount to cause the motor to turn and thus to move some object a required amount. In this example, the driver 9(E) would be a power amplifier circuit to provide the necessary voltage and current on line 9o to the assumed motor represented by device 10(D).
Also, the main input control signal A on line 2 from an outside module might be a voltage from some control switch or some variable resistance. If the device D(10) is already in the desired position, then the input signal A would be some zero value or some null value. Thus there would be no signal Y.sub.0 and no further motion involved in the device D(10).
However, if an outside person or some other motivating device wished to move the device 10(D) to a new position, this outside operator would turn the variable resistance knob or else flip certain switches in order to indicate a new position that was desirable. Then the input signal A would take on a new value. In the example of FIG. 1A the feedback signal C on line 10f1 is also some voltage which represents the position of the device D(10). Here then, the functional difference generator 4(G) examines both signals A and C. If these signals are the same, then the device D(10) must already be where it is required to be and thus the signal Y.sub.0 would be=0. However, if a new position is required, then A and C will differ, and Y.sub.0 will represent some "difference" voltage. The driver 9(E) then amplifies the signal Y into an output signal Y.sub.0 which is used to motivate or move the device D(10). As the device D(10) moves, it will cause a feedback signal C on line 10f1 to subtract from the input signal A until soon again the signal Y.sub.0 is again equal to zero.
FIG. 1A also shows a second feedback signal designated C1 on line 10f2. This is done so that some control systems can provide multiple levels of feedback control. In the above example of FIG. 1A, if the C feedback signal involves some positional measurement, then the signal C1 might be some "velocity" measurement. Thus the control system 8(H) could then control how fast that the device D(10) moved to the desired position.
FIG. 1A is a basic simple control system description. The detailed disclosure herein describes a control system for controlling the frequency of a variable frequency clock system. As will be indicated in the subsequent disclosure, all but a very tiny portion of the control system will be found to be implemented in digital (and not analog) circuitry. Further, most of the circuitry can be implemented in simple digital logic within a programmable device such as a Field Programmable Gate Array (FPGA).
FIG. 1B is a generalized overview of the environment involved in the receiver module which is the focus of the present disclosure.
The origin, or transmitter end of the data stream can be a long-distance, miles away from the receiver end, where the clock re-creation occurs as discussed in the present disclosure. There is no clock signal connecting the two remote locations, that is to say, the transmitter and the receiver. The only connection is a data stream, that is to say, a serial data stream which can very in the rate of data being transferred.
At the origin of the user data as seen in FIG. 1B, the actual user data is clocked at the frequency F.sub.o. This data frequency could be any number of values, but, for example, it might be a 155 MHz serial clock rate, which would be the equivalent of 19.4 MHz byte-wise. At the transmitter origin end, for the sake of proper transport, there is additional information (headers) which are inserted periodically between blocks of user data. Thus, since more information must be transmitted beyond that of the original user data, the serial data stream between the transmitter and the receiver is actually transmitted at a frequency somewhat greater than F.sub.o.
At the receiving end of FIG. 1B, there is seen to be a serial data stream running at the transmitted frequency of "F.sub.0 +" which is extra for the headers. The clock data recovery circuit 30 (also shown in FIG. 6) derives this clock from the data stream after which it is designated as I.sub.f. Thus, I.sub.f is the rate for all the received information, that is to say, both the user data and the extra headers. The receiver logic of FIG. 1B (which is detailed in FIG. 6) will strip away the headers and then re-create the actual user data clock rate F.sub.r. This frequency rate F.sub.r will then be "equal" to the original clock F.sub.o which originated on the other end of the transport system at the transmitter location of FIG. 1B.
As a further note, the transported data stream is "bit serial" and contains both the original user data, plus approximately a 1% of additional information in the headers. At the receiver end, the system deals with "parallel" versions of these clocks, where the system has converted the serial data, as a series of bits, to "bytes" to permit the system to work with slower clock rates. As a typical example of the frequencies involved, the original user data clock rate on a serial bit basis, might be 155 MHz. The original user data clock rate on a "byte" basis using the original frequency F.sub.o could be 19.4 MHz. The transmitter rate, together with the headers on a serial bit basis, would involve a rate of 156.55 MHz.
At the receiver end, the receiver recovered clock on a byte basis, of the frequency I.sub.f, could be 19.57 MHz, while the re-created user clock rate on a byte basis would have the frequency F.sub.r of 19.4 MHz.
As will later be seen in the subsequent description, the re-created user clock rate F.sub.r will operate to keep the FIFO 28 about the normal HALF-FULL position, which is designated as the optimum condition for operations.